Generally, since the operation speed of main memory unit is lower than that of CPU (Central Processing Unit) and a distance between the CPU and the main memory unit is large, it takes a long processing time for the CPU to obtain data from the main memory unit when a main memory unit access occurs.
For this reason, the current trend is toward a system equipped with a cache memory between an instruction computing unit executing and processing instruction control and arithmetic control in a CPU and a main memory unit.
Since the cache memory has a smaller storage capacity but operates at a higher speed than the main memory unit, and is closer to the instruction computing unit than the main memory unit, the instruction computing unit can fetch data in a much shorter time than accessing to the main memory unit.
Next, MMU (Memory Management Unit) will be mentioned. In an SPARC (registered trademark) architecture, for example, the OS (Operating System) manages a translation table to convert a virtual address into a physical address, and stores part of entries as entries each composed of a pair of a virtual address (TTE-Tag) called TTE (Translation Table Entry) and a physical address (TTE-Data) in a TSB (Translation Storage Buffer; address translation table) on the main memory unit.
Further, the OS stores part of these entries in a TLB (Translation Lookaside Buffer) in an MMU.
TSB has a large capacity but takes a long time to be accessed from the instruction computing unit, whereas TBL has a small capacity but can be accessed from the instruction computing unit at a high speed.
In a system having such TSB and TLB, when a designated virtual address is not registered on the TLB in the MMU, an MMU-MISS-TRAP (MMU miss; TLB miss) occurs.
On such occasion, the instruction computing unit reports the OS of this MMU-MISS-TRAP. The OS having received this report requires the instruction computing unit in the CPU to perform memory access processing, whereby the instruction computing unit in the CPU executes the memory access processing, as shown in a flowchart (steps S100 through S118) in FIG. 9 and a time chart (T1 through T33) in FIG. 10. Incidentally, each of T1 through T33 in FIG. 10 indicates processing unit time period by the instruction computing unit in the CPU.
In practice, the instruction computing unit starts a memory access based on a virtual address (step S100 in FIG. 9), and retrieves an entry which is a pair of the virtual address and a physical address corresponding to this virtual address from the TLB (refer to step S101 in FIG. 9 and T1 in FIG. 10).
Here, when the entry containing this virtual address is registered on the TLB (namely, when an MMU-MISS-TRAP does not occur; No route at step S102 in FIG. 9), the instruction computing unit performs retrieval from a cache memory by using the physical address in order to obtain data indicated by a physical address corresponding to the retrieved virtual address (step S103 in FIG. 9).
When a cache entry containing this data is registered on the cache memory (Yes route at step S104 in FIG. 9), the instruction computing unit reads the data, completes the memory access (step S105), and terminates the processing.
On the other hand, when a cache entry composed of a pair of the physical address and the data is not registered on the cache memory (No route at step S104 in FIG. 9), the instruction computing unit has a main memory unit access by using the physical address, enters data at this physical address into the cache memory (step S106 in FIG. 9), and again starts processing by using the virtual address (step S107 in FIG. 9; namely, returns to the above step S100).
By the way, when the entry of a pair of the retrieved virtual address is not registered on the TLB (that is, when an MMU-MISS-TRAP occurs; refer to Yes route at step S102 in FIG. 9 and T2 in FIG. 10), the OS having received a report of MMU-MISS-TRAP requires the instruction computing unit to perform a process from steps S108 to S118 to be described later in FIG. 9.
In practice, the instruction computing unit sets the virtual address at which the MMU miss occurs in the register, generates a virtual address on the TSB (hereinafter referred to as a TSB virtual address) corresponding to the virtual address on the basis of this virtual address, sets the TSB virtual address in the register, then reads the virtual address and the TSB virtual address (refer to steps S108 and S109 in FIG. 9 and T3 to T8 in FIG. 10).
Incidentally, a process of setting the virtual address in the register and a process of generating a TSB virtual address and setting the TSB virtual address in the register are executed during a time period between T2 to T3 in FIG. 10.
Next, a relationship between a virtual address and a TSB virtual address will be mentioned. As described above, an entry composed of a pair of a virtual address and a TSB virtual address is retained in a TSB on a main memory unit, an address on the TSB at which the entry of the pair of the virtual address and the physical address is retained is a TSB physical address, and a virtual address corresponding to this TSB physical address is a TSB virtual address. Further, in this MMU, an entry of a pair of the TSB virtual address and the TSB physical address is registered on and retained in a TLB.
The instruction computing unit then starts a memory access by using a read TSB virtual address (step S110 in FIG. 9), and retrieves an entry of a pair of the TSB virtual address and a TSB physical address corresponding to this virtual address from the TLB (refer to step S111 in FIG. 9 and T9 in FIG. 10). When the entry is retrieved from the TLB (when the entry is hit) (refer to step S112 in FIG. 9 and T10 in FIG. 10), the instruction computing unit performs retrieval from the cache memory by using this TSB physical address (refer to step S113 in FIG. 9 and T11 in FIG. 10).
Here, when an entry of a pair of the TSB physical address and data (TTE-TAG/Data; a pair of a virtual address and a physical address) retained on the main memory unit indicated by this TSB physical address is retrieved (hit) from the cache memory (Yes route at step S114 in FIG. 9), the retrieved entry is entered into the TLB (step S115 in FIG. 9), whereby an entry of a pair of the virtual address, which has been retrieved at the above step S101 and at which the MMU miss has occurred at the above step S102, and a physical address corresponding to this virtual address is entered into the TLB. The instruction computing unit again starts a memory access by using this virtual address (step S116 in FIG. 9; namely, returns to the above step S100).
On the other hand, when a cache entry of a pair of the TSB physical address and data is not registered on the cache memory (that is, when a cache memory miss occurs; refer to No route at step S114 in FIG. 9 and T12 in FIG. 10), the instruction computing unit has an access to the main memory unit by using the TSB physical address (refer to step S117 in FIG. 9 and T13 in FIG. 10), reads a pair of this TSB physical address and data from the main memory unit, enters the pair of the physical address and data into the cache memory (refer to T14 in FIG. 10), and again starts a memory access by using this TSB physical address (refer to step S118 in FIG. 9 and T15 and the following process in FIG. 10; namely, returns to the above step S110).
Meanwhile, the process at T15 to T22 in FIG. 10 corresponds to the above-described steps S110 to S116 in FIG. 9, the process at T23 to T28 in FIG. 10 corresponds to the above-described steps S100 to S104, S106 and S107 in FIG. 9, and the process at T29 to T33 in FIG. 10 corresponds to the above-described steps S100 to S105 in FIG. 9.
There have been proposed various kinds of techniques coping with occurrence of a translation miss (TLB miss) in TLB (refer to patent documents 1 to 3 below, for example).    Patent Document 1: Japanese Patent Application Laid-Open Publication No. 2000-112821    Patent Document 2: Japanese Patent Application Laid-Open Publication No. H02-285440    Patent Document 3: Japanese Patent Application Laid-Open Publication No. H02-178750